The present application claims priority to Japanese Patent Application No. 2002-88164 filed Mar. 27, 2002, the entire content of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a circuit board on which an integrated circuit having multiple power supply terminals is mounted.
2. Description of the Related Art
As the operating frequencies of circuit boards on which integrated circuits (ICs) are mounted have increased in recent years, reduction in electromagnetic radiation noise (EMI noise) has become a particular issue. In one conventional method to reduce EMI noise, a device, e.g. bypass condensers are connected between the integrated circuit""s power supply terminals and power supply plane and near the power supply terminals to bypass high-frequency power supply noise to the ground.
When reducing noise using bypass condensers, a bypass condenser is ideally located near each power supply terminal in the case of a circuit board on which is mounted an application-specific IC (ASIC) such as an integrated circuit that has multiple power supply terminals.
However, given that the arrangement of power supply terminals in an ASIC or the like is generally random, and is determined without consideration of the allocation of bypass condensers on the board, an increase in the number of bypass condensers leads to an increase in the component cost, etc., with the result that it is impractical to connect a bypass condenser to every power supply terminal. On the other hand, if there is a power supply terminal to which no bypass condenser is connected, common mode noise caused due to the high-speed switching operation of the ASIC or the like leaks to the power supply plane, thereby increasing the amount of EMI noise radiated from the circuit board.
A main object of the present invention is to provide a circuit board that can reduce noise while limiting the number of bypass condensers.
In order to attain this and other objects, according to one aspect of the present invention, the circuit board includes an outer layer on which an integrated circuit having multiple power supply terminals is mounted; a first power supply plane that is formed on a layer that is different from the outer layer, and receives power supply externally; a second power supply plane that is formed on the same layer as the first power supply plane but has a gap that terminates the electric connection with the first power supply plane; first power supply patterns that are formed on the outer layer and are electrically connected to the first power supply plane and the second power supply plane; bypass condensers that are disposed between the first power supply patterns and the ground; and second power supply patterns that are electrically connected to the second power supply plane and the power supply terminals.
Using the construction described above, at least some of the power supply terminals included in the integrated circuit are connected to the second power supply patterns. Consequently, bypass condensers need not be individually assigned to these power supply terminals, enabling the number of bypass condensers to be limited. In addition, because the leakage of noise from the power supply terminals to the first power supply plane can be reduced by the bypass condensers, noise reduction can be achieved as well.
It is preferred that the ground be disposed on a ground layer that is separate from the layer on which the first power supply plane and the second power supply plane are disposed, as well as from the outer layer on which the first power supply patterns and the second power supply patterns are disposed, such that the ground layer faces the second power supply plane. This is preferred because forming a capacitance between the ground layer and the second power supply plane permits a noise reduction effect to be obtained.
It is further preferred that the ground layer be disposed between the layer on which the first power supply plane and the second power supply plane are disposed and the outer layer. This is preferred because a further radiation noise reduction effect can be obtained based on the shielding effect of the ground layer.
In addition, it is preferred that the second power supply plane be disposed at a location that corresponds to the bottom of the integrated circuit and that the abovementioned gap be disposed along the outer circumference of the integrated circuit. This is the empirically preferred actual configuration of the second power supply plane.
Moreover, multiple multi-layer condensers having different capacitances may be mounted on the outer layer as the bypass condensers, and the condensers may be connected in a parallel fashion between the first power supply patterns and the ground such that the condensers closer to the first power supply plane have a higher capacitance.
When disposed such that the effect of the pattern inductor component from the integrated circuit to the bypass condenser is minimized, low-capacitance bypass condensers can reduce the deterioration in their high-frequency characteristics and offer an attenuation effect at a higher frequency.
The invention itself, together with further objects and attendant advantages, will best be understood by reference to the following detailed description taken in conjunction with the accompanying drawings.